Amiga OS 4.2x? "responsiveness" and protected memory

Hello everyone,

i read an interesting discussion on Amiganews.it (http://amiga.ikirsector.it/forum/viewtopic.php?f=37&t=17634) about an eventual memory protection implementation in future AmigaOS releases. The question is: will such implementation causes a general slowdown in AmigaOS reactivity or responsiveness?

There are no plans to make AmigaOS less responsive or slow it down.

It's true that adding more features "under the hood" (e.g. protected memory, SMP etc) will slow things down, but with the speed of modern CPUs, you won't notice. Don't think that because OSes like Windows, Linux and OS X have memory protection and are often very unresponsive, that those are cause and effect; they're not. If you look at RT kernels and many other microkernels (e.g. QNX) they can be incredibly responsive, while still offering such features.

In other words, don't worry!

SMP will slow things down?

Quote:

@

"There are no plans to make AmigaOS less responsive or slow it down."

Hehe.

glad to hear you say this.

What "technically" in a protected memory architecture could slowdown responsiveness?

Just curious. Maybe the check if a certain memory area is already in use? Searching for a free area?

@broadblues

Of course - any added complexity will slow things down. On a single core system you don't need to worry about arbitration of cores.

Of course the increase in speed far outweighs the decrease, but nonetheless, technically speaking, SMP slows things down for a single task running on a single core (which is what affects responsiveness).

I think what the original poster was worried about was that all the added bells and whistles would make AmigaOS feel like Windows - it won't. :)

The reason memory protection *could* slow things down is that the best memory protection makes copies of every message sent between two tasks, where-as AmigaOS only passes a message pointer between tasks. But it's not clear to me whether this will ever be an issue (it would require a radical redesign of message passing in AmigaOS).

It might be possible (depending on modern MMUs and what they can do - I'm no longer an expert in the field) to set up the MMU to handle the passing of the message from one address space to another, translating address pointers within the message as it does. If that task could be done in hardware, the additional latency could be reduced to a single ALU cycle.

The main problem (as you well know) is that some addresses have to be changed (those relative to the tasks concerned) and some don't (those relative to the system). Somehow the MMU has to be shown which addresses to change and which to treat as immutable data.

We used to do it back in the 80's with DEC hardware, so it should still be possible with hardware that is thirty years more advanced. However, a lot of features of the old CPUs have been dropped in modern microprocessors to save money, (eg multiple-level interrupts), so it may not be possible these days.