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Qemu Pegasos II interrupts issue
Home away from home
Joined: 2007/1/26 21:48Last Login
: 11/19 3:39
From New Zealand
Group:
Registered Users
I remember some previous discussions about potential problems with the interrupt emulation (at least for the Pegasos-II). Well, I've spotted something in my logs while trying to track down random freezes:
Here's a trace when the driver(s) receives an interrupt:
pic_update_irq master 0 imr 45 irr 2 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
The trace above occurs for every received interrupt (although it is different early on).
Then, something goes wrong, and I see:
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
Once this new pattern starts, then the drivers no longer get any interrupts. The last thing I see before it goes wrong, is the VirtioGPU driver indicating that the interrupt belongs to another device. Previous instances of the interrupt being passed on to another device cause no trouble, so I'm not sure why it suddenly starts failing. I do know that no more interrupts are received.**
Perhaps others could try tracing the IRQ behaviour as well. You need to add the following to the qemu command line: --trace "*update_irq"
Hans
** For testing, I put the VirtioGPU's interrupt at the highest priority. So it gets to see all interrupts on the assigned IRQ number, including ones meant for another device. The interrupts stop coming...
Re: Qemu Pegasos II interrupts issue
Just popping in
Joined: 2022/7/4 10:37Last Login
: Today 17:18
From Italy
Group:
Registered Users
Hi Hans.
When I wrote to ask you about the virtio driver.
I thought you would never do it.
I'm happy because I know you'll make it in the end.
I don't know if this will be helpful to you.
But you can monitor the qemu console
https://en.wikibooks.org/wiki/QEMU/Debugging_with_QEMU
Re: Qemu Pegasos II interrupts issue
Just can't stay away
Joined: 2023/4/7 6:13Last Login
: Yesterday 18:15
From Deutschland
Group:
Registered Users
@Hans I'm not sure how others can help with testing. Is it just referring to Qemu/GPU passthrough (real graphics card) or interrupt emulation in general with virtio-gpu-pci? I'm also glad they are still working on this driver and I hope they or others make it available sooner or later in whatever form. There have not been many changes for Balaton's Pegasos2 machine lately, as it already works very well and there have been no bugs that we could have reported. It's a bit off topic, but I was able to compile Qemu for the first time with VirGL support as there have been a lot of changes recently. The Qemu 9 freeze has already started. There will be no more major bug fixes for Qemu 9, it's more minor things that can be fixed. I hope Balaton reads something here and maybe can write us something more about it.
MacStudio ARM M1 Max Qemu//Pegasos2 AmigaOs4.1 FE / AmigaOne x5000/40 AmigaOs4.1 FE
Re: Qemu Pegasos II interrupts issue
Just can't stay away
Joined: 2006/12/1 19:07Last Login
: 11/16 10:57
From Germany
Group:
Registered Users
@Hans Try using AmigaOne XE or Sam460 emulation instead, IIRC the Pegasos2, emulation as well as real hardware, uses the same IRQ for nearly all hardware, for example the same IRQ is used for all PCI slots and maybe even for onboard devices like VIA PATA and USB, but next to no AmigaOS 4.x driver supports such shared IRQs. On the AmigaOne XE (and probably Sam460 as well, but I don't know enough about it), real and emulation, each PCI slot and onboard device uses a different IRQ number instead.
Re: Qemu Pegasos II interrupts issue
Just can't stay away
Joined: 2023/4/7 6:13Last Login
: Yesterday 18:15
From Deutschland
Group:
Registered Users
@Hans
I'm not sure if it's helpful, but I recorded it with "--trace "*update_irq "and sm_502.
Sys:Devs/Monitor/SiliconMotion 502 Interuppt is set to "yes"
Log:
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
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pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0
pic_update_irq master 1 imr 0 irr 1 padd 0pic_update_irq master 0 imr 237 irr 16 padd 0
pic_update_irq master 1 imr 251 irr 5 padd 0
pic_update_irq master 1 imr 251 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 173 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 64 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
I have abbreviated it a little because it basically always repeats the same thing. I'll test it tomorrow under the AmigaOneXe machine maybe there will be other results.
Tested with Qemu Master 9 freeze
MacStudio ARM M1 Max Qemu//Pegasos2 AmigaOs4.1 FE / AmigaOne x5000/40 AmigaOs4.1 FE
Re: Qemu Pegasos II interrupts issue
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@Hans Im using my build of v9.0.0-rc0 on windows, and I have tried peg2, amigaone and sam460 in qemu and have not seen the same issue. what version is your qemu build, as some irq updates balaton wrote for the southbridge were commited at the end of November 2023.
Re: Qemu Pegasos II interrupts issue
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@Joerg I was thinking of trying the A1-XE emulation instead. The Pegasos-II does indeed share a single IRQ line over multiple devices. That's just a workaround, though. If there is an IRQ emulation issue, then we want to figure out what it is and get it fixed. @Maijestro Did you get any device failure during that time? For example, the ethernet suddenly stops working. What we're looking for is a change in IRQ behaviour when something goes wrong... @derfs I'm currently using a self-compiled v8.2.1. No idea if Balaton's IRQ updates are included or not. Hans
Re: Qemu Pegasos II interrupts issue
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@Hans
I don't know if this could be an issue with emulation or a bug in AmigaOS. If you can reproduce the same with amigaone then it's more likely to be an issue in QEMU. If only happens on pegasos2 then it may be related to shared interrupts which may not be handled well in AmigaOS according to joerg so it could be a bug in AmigaOS that may need to be fixed to improve this. So testing with amigaone would help to locate the problem. Also sam460ex uses different interrupt controller so trying that too might also help. Between 8.2 and 9.0 there were no changes to irq handling on pegasos2 and amigaone so probably it's the same with 8.2.1 but using the latest QEMU version may help to make sure you don't debug something that was already fixed. I can't tell from the logs what could this be, I don't know much about PIC or it's emulation in QEMU, I did not write that part just using the already existing emulation that's well tested on PC machines and others using an ISA PIC so at least the functions used by Linux and Windows should not have bugs in it. Unless AmigaOS relies on some obscure feature of this chip or something that's specific to pegasos2 then maybe it's more about how AmigaOS handles the interrupts than an emulation issue. Could this be something related to not handling spurious interrupts correctly in AmigaOS? I mean something like described here:
https://forum.osdev.org/viewtopic.php?f=1&t=32722 Also in my understanding if multiple devices share an interrupt the interrupt handler should check each possible source and not ack the interrupt if none of the sources have active interrupt to avoid spurious interrupts.
Edited by balaton on 2024/3/21 13:53:25 Edited by balaton on 2024/3/21 13:55:29
Re: Qemu Pegasos II interrupts issue
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@joerg
Quote:
Try using AmigaOne XE or Sam460 emulation instead, IIRC the Pegasos2, emulation as well as real hardware, uses the same IRQ for nearly all hardware, for example the same IRQ is used for all PCI slots and maybe even for onboard devices like VIA PATA and USB, but next to no AmigaOS 4.x driver supports such shared IRQs. By the way, the IRQ setup on pegasos2 is just because the firmware sets it up that way. If AmigaOS prefers a different setup it could change it and configure it the way it wants but it does not. So if interrupt sharing cannot be fixed in AmigaOS for some reason then it could configure devices to not share the interrupt (although there may be more devices than free interrupts so some sharing might be needed).
Re: Qemu Pegasos II interrupts issue
Posted on:
3/21 15:00
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@balaton
Quote:
Also in my understanding if multiple devices share an interrupt the interrupt handler should check each possible source and not ack the interrupt if none of the sources have active interrupt to avoid spurious interrupts. AmigaOS supports only emulated IRQ. The driver is responsible for acknowledging the interrupt directly to the hardware.
The only administration for AmigaOS is to keep track of IRQ end messages versus interrupt vectors.
Re: Qemu Pegasos II interrupts issue
Posted on:
3/21 15:20
#11
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@Hans
Quote:
Did you get any device failure during that time? For example, the ethernet suddenly stops working. What we're looking for is a change in IRQ behaviour when something goes wrong...It was not directly a fault caused by the device. It just shows the "trace" from the start of the machine until the workbench is built.
So I don't think it was helpful. Sorry
But I can reproduce network failures and record the recording if that can be helpful. But even that probably won't help, as only the network is affected and everything else (sound/graphics etc.) will continue to work after the network has lost the connection.
MacStudio ARM M1 Max Qemu//Pegasos2 AmigaOs4.1 FE / AmigaOne x5000/40 AmigaOs4.1 FE
Re: Qemu Pegasos II interrupts issue
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@balaton
Quote:
I don't know if this could be an issue with emulation or a bug in AmigaOS. That's certainly possible. However, if real hardware devices are working properly on a real Pegasos-II, but not in QEMU, then it's unlikely (but still possible).
Quote:
If you can reproduce the same with amigaone then it's more likely to be an issue in QEMU. If only happens on pegasos2 then it may be related to shared interrupts which may not be handled well in AmigaOS according to joerg so it could be a bug in AmigaOS that may need to be fixed to improve this. I'm not convinced that Joerg is correct. After all, real Pegasos-II also shares the same interrupt between multiple devices. If shared interrupts were a problem, then we should see people with real Pegasos-IIs complaining about it.
The AmigaOS kernel can definitely handle shared interrupts. Interrupt handlers on the same IRQ number are put in a priority sorted list. Each handler is called one by one, until one of them returns TRUE, indicating that it has processed and acknowledged the interrupt. So long as all handlers in the chain are written properly, everything works fine.
It's quite possible for a faulty driver to either return TRUE when the interrupt didn't belong to it, or to fail to acknowledge an interrupt that does belong to it. Either case would cause an instant lockup with level triggered interrupts, because the interrupt line doesn't get cleared until the interrupt is properly acknowledged.
Quote:
Between 8.2 and 9.0 there were no changes to irq handling on pegasos2 and amigaone so probably it's the same with 8.2.1 but using the latest QEMU version may help to make sure you don't debug something that was already fixed. I'll try updating to v9, and see what happens. Testing the A1-XE version will take more time...
Quote:
I can't tell from the logs what could this be, I don't know much about PIC or it's emulation in QEMU, ... Yeah, all I have so far is a clear change in behaviour. I haven't managed to track down how the PIC emulation code triggers an interrupt in the emulated PowerPC. That's another potential point at which something could go wrong (I'm guessing that x86/x64 emulation is much more tested than PPC).
Quote:
Could this be something related to not handling spurious interrupts correctly in AmigaOS? I mean something like described here: https://forum.osdev.org/viewtopic.php?f=1&t=32722 Also in my understanding if multiple devices share an interrupt the interrupt handler should check each possible source and not ack the interrupt if none of the sources have active interrupt to avoid spurious interrupts. No idea. I'll try to see if I can get interrupt related debug output out of the AmigaOS kernel. If the kernel is receiving interrupts after the driver has stopped receiving them.
This one problem is turning into a time-sucking rabbit hole...
Hans
Re: Qemu Pegasos II interrupts issue
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@Maijestro
Quote:
But I can reproduce network failures and record the recording if that can be helpful. But even that probably won't help, as only the network is affected and everything else (sound/graphics etc.) will continue to work after the network has lost the connection. No harm in trying to record an ethernet device failure, to see if there's a noticeable change.
Hans
Re: Qemu Pegasos II interrupts issue
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@all Same behaviour with v9.0.0-rc0. Hans
Re: Qemu Pegasos II interrupts issue
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@Hans
Quote:
I'm not convinced that Joerg is correct. After all, real Pegasos-II also shares the same interrupt between multiple devices. If shared interrupts were a problem, then we should see people with real Pegasos-IIs complaining about it. Would require that there are people using AmigaOS 4.1 on a real Peagaos2
One of the Friedens had a Pegasos2 for porting AmigaOS 4.x to it and probably Stéphane (peg2ide.device), but IIRC there was no single OS4 beta tester who had one as well.
I guess there are currently 1-5 users using AmigaOS 4.1 on a real Pegasos2 (kas1e has one) and about 20-30 using it with a QEmu emulated Pegasos2.
There are definitely some broken HW drivers not checking if it's an interrupt for their own hardware and always return TRUE in their interrupt handler function.
On the AmigaOne SE/XE/µA1 (and maybe Sam440/460 as well), no matter if real or emulated, where nearly all HW uses different IRQ numbers such broken drivers may still work, but not on the Pegasos2 with everything using the same, shared IRQ.
But even if all HW drivers would work correctly: What happens if there is an interrupt from 2 different devices at the same time?
With (nearly) every device using a different IRQ, like on the AmigaOne SE/XE/µA1, it's no problem: The interrupt handler functions are in different AmigaOS interrupt lists, one per IRQ number (IIRC the AmigaOS interrupt numbers/lists are ISA/PCI IRQ numbers +16 or +32).
But on the Pegasos2 I guess the interrupt handler of the first driver in the single interrupt list handles the interrupt and returns TRUE, which means no other interrupt handler function in the list gets called.
To make it work with shared IRQs like on the Pegasos2 the interrupt handler of all drivers may always have to return FALSE, even if it was an interrupt for their hardware they handled, to make sure the interrupt handler functions of other devices in the same interrupt list get called as well.
Re: Qemu Pegasos II interrupts issue
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@joerg
Quote:
Would require that there are people using AmigaOS 4.1 on a real Peagaos2 Wow! All that work for so few people...
@all
I have no way to check interrupts from the kernel. However, in qemu I added a print statement in pegasos2_pci_irq(). Under normal operation, this happens:
pegasos2_pci_irq : 1 , level : 1
pic_update_irq master 0 imr 45 irr 2 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
IRQ !
pegasos2_pci_irq : 1 , level : 0
pegasos2_pci_irq : 1 , level : 1
pic_update_irq master 0 imr 45 irr 2 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
IRQ !
pegasos2_pci_irq : 1 , level : 0
The IRQ! is from my driver. So the Pegasos-II's interrupt line is being set. The interrupt handler is triggered, and the interrupt level goes to 0, and the whole process can start again.
Then something goes wrong:
pegasos2_pci_irq : 1 , level : 1
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 1 imr 249 irr 3 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 0 imr 45 irr 128 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
pic_update_irq master 1 imr 249 irr 5 padd 0
The interrupt gets set, but isn't passed on. From here on out, the interrupt line doesn't go low any more.
I'm still tracing execution down the line. I'm wondering if something is supposed to be level triggered, but is operating in edge triggered mode only. In level triggered mode, if the IRQ line is still set, then the interrupt handler should be retriggered. The A1-XE was set to be level triggered. No idea how the Pegasos II is set up.
Hans
Edited by Hans on 2024/3/23 7:46:21 Edited by Hans on 2024/3/23 7:49:48
Re: Qemu Pegasos II interrupts issue
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@all I've traced it further, through: - mv64361_update_irq() - PPC6xx_INPUT_INT - ppc_set_irq() - ppc_maybe_interrupt() - cpu_interrupt() ppc_maybe_interrupt() is calling cpu_interrupt() even after my driver stops getting interrupts. It looks like the interrupts are getting through, but something is going wrong within the emulation. I'll try the emulated AmigaOne next... Hans
Re: Qemu Pegasos II interrupts issue
Posted on:
3/22 13:45
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@joerg
Quote:
But even if all HW drivers would work correctly: What happens if there is an interrupt from 2 different devices at the same time? With (nearly) every device using a different IRQ, like on the AmigaOne SE/XE/µA1, it's no problem: The interrupt handler functions are in different AmigaOS interrupt lists, one per IRQ number (IIRC the AmigaOS interrupt numbers/lists are ISA/PCI IRQ numbers +16 or +32). But on the Pegasos2 I guess the interrupt handler of the first driver in the single interrupt list handles the interrupt and returns TRUE, which means no other interrupt handler function in the list gets called. To make it work with shared IRQs like on the Pegasos2 the interrupt handler of all drivers may always have to return FALSE, even if it was an interrupt for their hardware they handled, to make sure the interrupt handler functions of other devices in the same interrupt list get called as well. This might only be a problem with edge triggered interrupts but should not be a problem if IRQs are level sensitive. In the latter case the interrupt would be re-raised as long as there's a device requesting interrupt and the next handler would get a chance to handle it until all drivers ack their own interrupts. I think the default for the PIC is edge trigger but I know that on pegasos2 MorphOS sets it to level mode because it does so using an ancient method that wasn't emulated. This was found here:
https://lists.nongnu.org/archive/html/ ... ppc/2023-02/msg00401.html and was finally fixed with this patch:
https://lists.nongnu.org/archive/html/ ... ppc/2023-03/msg00341.html . So the question is if AmigaOS uses level sensitive interrupts or does anything to set the PIC for that? If not then maybe the pegasos2 firmware has some setup for this that is relied upon but when booting without firmware we miss that setup. To verify this maybe @Hans could also try reproducing it with -bios pegasos2.rom and see if there's some difference with that (or compare initial setup of PIC registers with -trace enable="pic*" with pegasos2.rom and without to see if there's some setup missing). Ideally AmigaOS should set up the hardware the way it likes but if this is something done by the pegasso2 firmware we can emulate that when not using firmware (either in QEMU or BBoot).
Re: Qemu Pegasos II interrupts issue
Posted on:
3/22 13:59
#19
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@Hans Your logs don't make sense to me (although I don't know how it works nor how it should work so I'm only trying to make some guesses). I only see updates in the master PIC but IRQ9 which is used by all PCI and on-board devices on pegasos2 is on the slave PIC so where are the logs from that? Maybe something masked out IRQ2 on the master and hasn't reenabled it so the slave interrupts can no longer be raised? I don't know what are the bits in IMR (and too lazy to look it up now) but it seems to have more bits set when you get the problem. If you've traced that the interrupt reaches cpu_interrupt() then that should come back as an exception in qemu/target/ppc/excp_helper.c and it's not very likely to be lost there. You can get a log of all exceptions with -d int but it's usually too much logs to be useful. Are you sure the interrupts you see are from your PCI device and not from some other device? Another command that may be useful is 'info pic' in QEMU monitor that shows the PIC registers so you can check that as not all of them are logged in the trace output. If this could be caused by a buggy driver then maybe a way to debug it could be to disable them and enable one by one. So try without network, sound, usb first and then add them one by one in case one of those cause this to happen. I don't have any better idea to help with this.
Re: Qemu Pegasos II interrupts issue
Posted on:
3/22 14:02
#20
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@joerg
Quote:
Would require that there are people using AmigaOS 4.1 on a real Peagaos2 One of the Friedens had a Pegasos2 for porting AmigaOS 4.x to it and probably Stéphane (peg2ide.device), but IIRC there was no single OS4 beta tester who had one as well. I guess there are currently 1-5 users using AmigaOS 4.1 on a real Pegasos2 (kas1e has one) and about 20-30 using it with a QEmu emulated Pegasos2. @sailor has one too but she's probably too busy with her new A1222+ now. I think @flash had one too but maybe ran MorphOS on it more.
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