Quote:
alfkil wrote:
@derfs
Thanks for the input! So floats have to be 8 byte aligned, no...?
It seems though, that this could not possibly be related to a crash on a fmr instruction, so I guess I am back at the old drawing board...
Unlikely, but there is another problem with the fmr instruction on the Sam versus that on the earlier PPCs:
A number of the FP instructions exist in both a "recording" form and a non-recording form, based on the Rc bit (bit 31) in the instruction coding.
eg, fmr has a 0 in bit 31
fmr. has a 1 in bit 31
(the dot after the fmr is the usual assembler representation of the recording form)
If FP "recording", then bits 0..3 of the FPCSR are copied into the CR1 field of the Condition Register at the end of the instruction.
Unfortunately, the 440ep SOCs do not support the recording form of FP instructions (though they do support, or course, the similar recording form of the Fixed Point instructions).
As of PowerISA V2.02, the group or recording FP instrus has been separated out into a different "category" in the instruction set, so it is kosher for an embedded processor which supports FP not to support them.
I don't think they were used much, by my Modula-2 compiler was generating "fmr." in some places and I had to change that when my Sam arrived to get programs that used it not to crash.
Tom